| Submission Open for Jan-Dec-2024 |
| Last Date of Submission : |
| 20th, April-2024 |
| Acceptance Notification : |
After Peer Review |
| Last Date of Publication : |
| 30th, April-2024 |
Volume10 ISSUE 1 Call for Conference Special Issue Archive (Recent Update ISSUE)
| S.NO | TITLE | PAGE NO | DOWNLOAD | |
| IJVDCS 48 | Design and Implementation of AES Algorithm with UART Authors:HUMMA NOWSHEEN, B.VASU NAIK |
0274-0277 |
Download | |
| IJVDCS 49 | Implementation of Robust Encryption Algorithm for Wireless Communication Authors:P.PRASANTH, V.SWATHI |
0278-0281 |
Download | |
| IJVDCS 50 | Designing of DA Based Adding and Shifting, LUT Based Fir Filters on FPGA Authors:DHANASHRI KUNTURWAR, M.R.VARGANTWAR |
0282-0284 |
Download | |
| IJVDCS 51 | Design of High Speed BCD Adder using LUT Authors:MALLIREDDY SAI DEEPIKA, M.NARESH BABU |
0285-0289 |
Download | |
| IJVDCS 52 | Designing and Compare Analyses of Vedic Multiplier using Compressors and Reversible Logic Gats used Vedic Multiplier Authors:DASARI SRAVANTHI, B.VASU NAIK |
0290-0293 |
Download | |
| IJVDCS 53 | Radix-2k Feed Forward FFT Architectures Authors:K.KIRAN KUMAR, M.MADHU BABU |
0294-0298 |
Download | |
| IJVDCS 54 | Design and Comparison of Effective Area Efficient Architectures for CSLA using CLA Authors:CH. MANOJ KUMAR, K. MURALI |
0299-0304 |
Download | |
| IJVDCS 55 | Design and Simulation of Low Power Approximate Adders using Different Technologies Authors:U.P. OBULESU, SYAMALA DEVI |
0305-0310 |
Download | |
| IJVDCS 56 | Power Reduction of Pulse Triggered Flip Flop using Enhanced Pulse Authors:P. YASWANTH, KANTE MURALI |
0311-0314 |
Download | |
| IJVDCS 57 | Implementation of Self-Calibrated DLL-Based Clock Generator Authors:REDDIGARI VINEELA, K.CHANDRA SEKHAR |
0315-0319 |
Download | |
